1. Field of the Invention
The present invention relates to the field of flash memory. More particularly, the present invention relates to a system and method for tracking the number of erased cycles in flash memory to assure that flash blocks nearing their erase cycle limit are not used.
2. Description of Related Art
Flash memory devices have become popular for applications requiring non-volatility and in-circuit programmability. Typically, flash memory devices contain separately erasable flash blocks; namely, each flash block can be erased independently of other flash blocks. In addition, each flash block is designed with a specific "erase cycle limit," being a maximum number of times that the flash block can be erased without an increased probability of experiencing unreliable operations. At the present time, the erase cycle limit of a flash memory device is approximately 100,000 erase cycles per flash block.
In many applications, this limit is well beyond the typical usage of the flash memory device, such as for example, a Basic Input/Output Systems (BIOS) application for a personal computer. However, in those applications supporting a large number of electronic transactions that need to be recorded or stored in the flash memory device, this limit might pose a problem. Examples of applications requiring a large number of erase cycles include digital cash registers, commercial transactions, and banking transactions. In those applications, electronic systems employing flash memory devices may be more vulnerable to sabotage or industrial attack by an intruder artificially generating a high number of transactions in an attempt to exceed the erase cycle limit of the flash memory. The reason for generating these transactions is that overly used memory may provide a better opportunity to successfully compromise the electronic system.
As shown in FIG. 1, in prior art flash memory architectures, a flash memory device 10 is typically partitioned into a number of separate flash blocks which can be individually erased. In this flash architecture, there are 16 flash blocks, each flash block 20.sub.1 -20.sub.16 having 64 kilobytes ("KB") of memory. Every bit of the flash blocks 20.sub.1 -20.sub.16 is placed in an initial ("SET") state. Flash memory device 10 is written by changing the state of a bit from its SET state to a desired state. The desired state may be the SET state or an opposite ("CLEAR") state. Typically, bits can only be changed from SET to CLEAR, or remain in the same state. Once a bit is changed from SET to CLEAR, it cannot be changed back to SET unless it is erased. Moreover, the erasure cannot be done for individual bits, rather it is done for the entire flash block 20.sub.y (y=1, 2 . . . or 16) which contains that bit. It is this erasure that creates wear on the flash block 20.sub.y. After some approximate number of erasures (e.g., 100,000 cycles), the flash block is not considered to be reliable.
It is therefore necessary to employ a scheme that keeps track of the number of erasures for specific flash blocks of a flash memory device, or a way to identify specific flash blocks in the flash memory device that are nearing their erase cycle limit. This information can then be used to ensure that such overly used flash memory blocks are not used for storing critical data.
One simple solution to the problem is to include a tracking capability in system software such that every time there is an erasure of the flash memory device, the software will increment a counter, dedicated to that particular flash block, and will store the value of the counter in the hard disk. However, this solution poses a number of problems. First of all, it would create a burden on the software that needs to be written to take into account the tracking capability. Secondly, the software itself might also be vulnerable to other attacks. It is more desirable to have a capability of keeping track of the erasures using hardware or firmware embedded within a flash memory device.